1. Field of the Invention
The present invention relates to a semiconductor device and memory in which a step-down voltage circuit that generates a voltage lower than a power supply voltage is mounted.
2. Description of the Related Art
A DRAM normally comprises a word (and the like)-driving thick film-type transistor and a logic section (and the like)-driving thin film-type transistor. Thin film-type transistor can be actuated using a voltage of the order of, for example, 2.5V, while a thick film-type transistor can be actuated using a voltage of the order of, for example, 3.3V. However, from the viewpoint of power consumption reduction, memory cells are operated using a voltage of the order of, for example, 1.8V. Thereupon, a step-down voltage circuit for stepping down a power supply potential VDD0 to, for example, 1.8V is required (for example, see Japanese Unexamined Patent Application Publication No. 2000-149565).
FIG. 18 is a diagram of a conventional memory and a step-down voltage circuit provided in the periphery thereof. As shown in FIG. 18, a step-down voltage circuit unit 110 comprises a power supply terminal 111 for supplying an external system power supply VDD0 of, for example, 3.3V, and step-down voltage circuits 112, 113. The power supply potential VDD0 is supplied without alteration to an I/O interface 31 and so on. In addition, a step-down voltage V1 obtained by stepping down of an external power supply DVV0 to, for example, 2.5V is supplied to a peripheral logic circuit 20. The step-down voltage circuit unit 110 comprises the step-down voltage circuit 112 for this purpose. The step-down voltage circuit 112 generates the step-down voltage V1 from the power supply potential VDD0. In addition, a memory cell 21 is supplied with an even lower step-down voltage V2 of, for example, 1.8V. The step-down voltage circuit unit 110 comprises the step-down voltage circuit 113 for this purpose. The step-down voltage circuit 113 generates the step-down voltage V2 from the power supply potential VDD0.
Meanwhile, as is described in cited Japanese Unexamined Patent Application Publication No. 2003-257181 (Takemura et al.) and as shown in FIG. 19, in an overdrive system, after a word line is activated and rises to a word line step-up voltage VPP a bit line is activated, whereupon a high-side bit line (T), to an array internal step-down voltage VDL, and a low-side bit line (B), to an earthed voltage VSS, are amplified. At this time, an overdrive startup pulse FASAP1T is generated whereupon, subsequent to the high-side bit line (T) having been spread to an overdrive voltage VDDA, a VDL sense amplifier startup signal FASAP1T is generated to stabilize it at the array internal step-down voltage VDL.
The power supply stepping down of a memory cell array can be achieved by the provision of a step-down voltage circuit. However step-down voltage circuit that uses a thick film transistor is required to generate a voltage lower than the high power supply voltage VDD0 in this way. Accordingly, there are associated problems of poor memory cell array responsivity and, in turn, increased current flow to the current mirror and large current consumption.
In addition, actualization of overdrive based on the provision of a step-down voltage circuit requires that the overdrive voltage be taken as the power supply potential and the normal voltage be taken as the step-down voltage. Accordingly, the step-down voltage circuit can only be configured from a VDD-compliant thick-film transistor which, as is described above, results in poor responsivity and is an impediment to improved speed thereof.